/*
    Copyright (c) 2007 Stefan Engelke <mbox@stefanengelke.de>

    Permission is hereby granted, free of charge, to any person 
    obtaining a copy of this software and associated documentation 
    files (the "Software"), to deal in the Software without 
    restriction, including without limitation the rights to use, copy, 
    modify, merge, publish, distribute, sublicense, and/or sell copies 
    of the Software, and to permit persons to whom the Software is 
    furnished to do so, subject to the following conditions:

    The above copyright notice and this permission notice shall be 
    included in all copies or substantial portions of the Software.

    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
    NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 
    HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 
    WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
    DEALINGS IN THE SOFTWARE.
*/

/* Bit Mnemonics */
#define MASK_RX_DR  6
#define MASK_TX_DS  5
#define MASK_MAX_RT 4
#define EN_CRC      3
#define CRCO        2
#define PWR_UP      1
#define PRIM_RX     0
#define ENAA_P5     5
#define ENAA_P4     4
#define ENAA_P3     3
#define ENAA_P2     2
#define ENAA_P1     1
#define ENAA_P0     0
#define ERX_P5      5
#define ERX_P4      4
#define ERX_P3      3
#define ERX_P2      2
#define ERX_P1      1
#define ERX_P0      0
#define AW          0
#define ARD         4
#define ARC         0
#define PLL_LOCK    4
#define RF_DR       3
#define RF_PWR      6
#define RX_DR       6
#define TX_DS       5
#define MAX_RT      4
#define RX_P_NO     1
#define TX_FULL     0
#define PLOS_CNT    4
#define ARC_CNT     0
#define TX_REUSE    6
#define FIFO_FULL   5
#define TX_EMPTY    4
#define RX_FULL     1
#define RX_EMPTY    0
#define DPL_P5	    5
#define DPL_P4	    4
#define DPL_P3	    3
#define DPL_P2	    2
#define DPL_P1	    1
#define DPL_P0	    0
#define EN_DPL	    2
#define EN_ACK_PAY  1
#define EN_DYN_ACK  0

/* Instruction Mnemonics */
#define R_REGISTER    0x00
#define W_REGISTER    0x20
#define REGISTER_MASK 0x1F
#define ACTIVATE      0x50
#define R_RX_PL_WID   0x60
#define R_RX_PAYLOAD  0x61
#define W_TX_PAYLOAD  0xA0
#define W_ACK_PAYLOAD 0xA8
#define FLUSH_TX      0xE1
#define FLUSH_RX      0xE2
#define REUSE_TX_PL   0xE3
#define NOP           0xFF

/* Non-P omissions */
#define LNA_HCURR   0

/* P model memory Map */
#define RPD         0x09

/* P model bit Mnemonics */
#define RF_DR_LOW   5
#define RF_DR_HIGH  3
#define RF_PWR_LOW  1
#define RF_PWR_HIGH 2

/********************************************************************************
 * The following commands and registers are derived from the NRF24L01 Datasheet
 */

/*
 * NRF24L01 commands
 */
#define NRF_COM_READREG                                         0x00      /* 0b000A AAAA read register  A AAAA    */
#define NRF_COM_WRITEREG                                        0x20      /* 0b001A AAAA write register A AAAA    */
#define NRF_COM_RX_PAYLOAD                                      0x61  /* Read RX-payload                          */
#define NRF_COM_TX_PAYLOAD                                      0xA0  /* Write TX-payload                         */
#define NRF_COM_FLUSH_TX                                        0xE1      /* Flush TX FIFO	*/
#define NRF_COM_FLUSH_RX                                        0xE2      /* Flush RX FIFO	*/
#define NRF_COM_REUSE_TX                                        0xE3  /* Reuse last transmitted payload          */
#define NRF_COM_ACTIVATE                                        0x50  /* Activate the features                   */
#define NRF_COM_R_RX_PL_WID                                     0x60      /* Read RX-payload width               */
#define NRF_COM_W_ACK_PAYLOAD                           				0xA8      /* 0b10101PPP valid from 000 to 101    */
#define NRF_COM_W_TX_PAYLOAD_NOACK      												0xB0      /* Disables AUTOACK on packet          */
#define NRF_COM_NOP                     												0xFF      /* NOP (No operation)	*/

/*
 * NRF24L01 registers
 */
#define NRF_REG_CONFIG       0x00                            /* Configuration Register	*/
#define NRF_REG_EN_AA        0x01                            /* Auto Acknowledgment */
#define NRF_REG_EN_RXADDR    0x02                            /* Enabled RX Addresses	*/
#define NRF_REG_SETUP_AW     0x03                            /* Setup of Address Widths  */
#define NRF_REG_SETUP_RETR   0x04                            /* Setup of Automatic Retransmission    */
#define NRF_REG_RF_CH        0x05                            /* RF Channel */
#define NRF_REG_RF_SETUP     0x06                            /* RF Setup Register 	*/
#define NRF_REG_STATUS       0x07                            /* Status Register	*/
#define NRF_REG_OBSERVE_TX   0x08                            /* Transmit observe register  */
#define NRF_REG_CD           0x09                            /* Carrier Detect	*/
#define NRF_REG_RX_ADDR_P0   0x0A                            /* Receive address data pipe 0                          */
#define NRF_REG_RX_ADDR_P1   0x0B                            /* Receive address data pipe 1                          */
#define NRF_REG_RX_ADDR_P2   0x0C                            /* Receive address data pipe 2                          */
#define NRF_REG_RX_ADDR_P3   0x0D                            /* Receive address data pipe 3                          */
#define NRF_REG_RX_ADDR_P4   0x0E                            /* Receive address data pipe 4                          */
#define NRF_REG_RX_ADDR_P5   0x0F                            /* Receive address data pipe 5                          */
#define NRF_REG_TX_ADDR      0x10                            /* Transmit address	*/
#define NRF_REG_RX_PW_P0     0x11                            /* Number of bytes in RX payload                        */
#define NRF_REG_RX_PW_P1     0x12                            /* Number of bytes in RX payload                        */
#define NRF_REG_RX_PW_P2     0x13                            /* Number of bytes in RX payload                        */
#define NRF_REG_RX_PW_P3     0x14                            /* Number of bytes in RX payload                        */
#define NRF_REG_RX_PW_P4     0x15                            /* Number of bytes in RX payload                        */
#define NRF_REG_RX_PW_P5     0x16                            /* Number of bytes in RX payload                        */
#define NRF_REG_FIFO_STATUS  0x17                            /* FIFO Status Register                                                         */
#define NRF_REG_DYNPD        0x1C                            /* Enable dynamic payload length                        */
#define NRF_REG_FEATURE      0x1D                            /* Feature Register */

/*
 * Status register masks
 */
#define NRF_STAT_RX_DR        0x40      /* Data ready RX FIFO interrupt                         */
#define NRF_STAT_TX_DS        0x20      /* Data sent interrupt                                  */
#define NRF_STAT_MAX_RT       0x10      /* Maximum number of TX retries                         */
#define NRF_STAT_RX_R_NO      0x0E      /* Data pipe number for payload                         */
#define NRF_STAT_TX_FULL      0x01      /* TX FIFO full flag                                    */

/*
 * FIFO status mask
 */
#define NRF_FIFO_TX_REUSE                                               0b01000000      /* Reuse lost sent data packet high             */
#define NRF_FIFO_TX_FULL                                                0b00100000      /* TX FIFO full flag                                                                    */
#define NRF_FIFO_TX_EMPTY                                               0b00010000      /* TX FIFO empty flag                                                                   */
#define NRF_FIFO_RX_FULL                                                0b00000010      /* RX FIFO full flag                                                                    */
#define NRF_FIFO_RX_EMPTY                                               0b00000001      /* RX FIFO empty flag                                                                   */

